A full adder differs from a half adder because:
Subtraction uses the ALU, not the adder design itself.
Correct — a full adder has 3 inputs: A, B, and carry-in.
A full adder handles 1-bit; 8 full adders chained form an 8-bit adder.
All logic can be built from NAND, but that's not what defines a full adder.
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Subtraction is done via two's complement addition. The adder itself still only adds.
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A single full adder: 1-bit A + 1-bit B + carry-in → sum + carry-out. Chain 8 for an 8-bit adder.
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NAND universality means any circuit can be built from NANDs. The defining feature of a full adder is the carry-in input.
A multiplexer (MUX) does what?
Amplification is an analog concept; digital MUX selects data.
That is an ADC (analog-to-digital converter).
Correct — a 2-to-1 MUX picks between two inputs based on a select bit.
That is a demultiplexer (DEMUX).
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A MUX is a digital selector. It picks one of N inputs based on select lines, not signal strength.
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ADC quantizes an analog voltage. MUX just routes one of several digital inputs to a single output.
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MUX = many-to-one. DEMUX = one-to-many. They are complementary devices.
A decoder with n select lines has how many outputs?
n outputs would only support n selected lines — not enough.
2n grows too slowly. A 3-line decoder has 8 outputs, not 6.
Correct — n select lines → 2ⁿ unique combinations → 2ⁿ outputs.
n² does not match. A 3-line decoder: 3²=9 ≠ 8.
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A decoder activates exactly one output per input code. With n lines there are 2ⁿ possible codes → 2ⁿ outputs.
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2×3=6 ≠ 8. The correct formula is 2ⁿ: each additional select line doubles the number of outputs.
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2³=8, not 3²=9. Outputs = 2ⁿ.
In a ripple-carry adder, the main speed limitation is:
XOR gates compute the sum bit but aren't the bottleneck.
Correct — each stage waits for carry-in from the previous, causing O(n) delay.
Voltage affects transistor speed but is not the architectural limitation of ripple-carry.
Bus width determines how many bits are transferred, not the adder's carry delay.
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The sum bit uses XOR, which is fast. The problem is each stage must wait for the carry from the previous stage to propagate.
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Ripple-carry delay is an architectural issue: serial carry propagation. Voltage is a physical concern, not the design bottleneck.
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Bus width affects bandwidth. Adder delay is determined by carry chain length.
A tri-state buffer outputs high, low, or:
Tri-state adds a third valid output state (high-Z), not an error.
Correct — the third state electrically disconnects the output from the bus.
Oscillation would be a fault condition, not the designed third state.
Digital logic uses positive supply voltages; negative output would be a fault.
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Tri-state buffers explicitly produce a high-impedance state when disabled — this is intentional and controlled.
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A properly designed tri-state buffer either drives 0, drives 1, or disconnects (high-Z). It does not oscillate.
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Standard CMOS logic swings between GND and VDD. Tri-state means high-impedance, not negative.